From 26f15d13ea9b7e92eaf2326909b202799797f440 Mon Sep 17 00:00:00 2001 From: b0hemia <50309975+b0hemia@users.noreply.github.com> Date: Mon, 24 Aug 2026 23:52:48 +1000 Subject: [PATCH 6/8] ddr: fix PHY PLL divisors 20/5 -> 8/4 for W63AH6NKB LPDDR3 400MHz (calibration root cause) --- arch/mips/cpu/xburst2/ddr_innophy.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/arch/mips/cpu/xburst2/ddr_innophy.c b/arch/mips/cpu/xburst2/ddr_innophy.c index b394dad..4c7b921 100755 --- a/arch/mips/cpu/xburst2/ddr_innophy.c +++ b/arch/mips/cpu/xburst2/ddr_innophy.c @@ -247,25 +247,22 @@ static void ddrp_pll_init(void) { unsigned int val; + /* PHY PLL divisors for W63AH6NKB LPDDR3 @400MHz: FBDIV=8, PDIV=4 (from tobunto X2000, + * matches the vendor SPL). The tree's stock 20/5 sets the wrong PHY clock -> training + * (CALIB_DONE) never converges. */ val = ddr_readl(DDRP_INNOPHY_PLL_FBDIV); val &= ~(0xff); - val |= 0x14; + val |= 0x8; ddr_writel(val, DDRP_INNOPHY_PLL_FBDIV); val = ddr_readl(DDRP_INNOPHY_PLL_PDIV); val &= ~(0xff); - val |= 0x5; + val |= 4; ddr_writel(val, DDRP_INNOPHY_PLL_PDIV); - /* ddr_writel(0x14, DDRP_INNOPHY_PLL_FBDIV); */ - /* ddr_writel(0x5, DDRP_INNOPHY_PLL_PDIV); */ -#ifdef DEBUG_READ_WRITE + /* toggle PLLPDEN via RMW (preserve other PLL_CTRL bits), as tobunto/vendor do */ ddr_writel(ddr_readl(DDRP_INNOPHY_PLL_CTRL) | DDRP_PLL_CTRL_PLLPDEN, DDRP_INNOPHY_PLL_CTRL); ddr_writel(ddr_readl(DDRP_INNOPHY_PLL_CTRL) & ~DDRP_PLL_CTRL_PLLPDEN, DDRP_INNOPHY_PLL_CTRL); -#else - ddr_writel(DDRP_PLL_CTRL_PLLPDEN, DDRP_INNOPHY_PLL_CTRL); - ddr_writel(0, DDRP_INNOPHY_PLL_CTRL); -#endif DDR_BOUND(ddr_readl(DDRP_INNOPHY_PLL_LOCK) & (1 << 3), 10 /*PLL_LOCK*/, ddr_readl(DDRP_INNOPHY_PLL_LOCK)); } -- 2.43.0