b0hemia
e0bc4785e9
Flashes the diskOS custom UI onto the FiiO Snowsky Disc over Ingenic mask-ROM USB, building the image from your own stock firmware. Runs from source via install.sh.
77 lines
3.3 KiB
Diff
77 lines
3.3 KiB
Diff
From 8f93e72bd6b1c770269ce746d401cebb063e71dc Mon Sep 17 00:00:00 2001
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From: b0hemia <50309975+b0hemia@users.noreply.github.com>
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Date: Mon, 24 Aug 2026 22:55:29 +1000
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Subject: [PATCH 2/8] =?UTF-8?q?ddr:=20add=20LPDDR3=20support=20(mr11=20fie?=
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=?UTF-8?q?ld,=20LPDDR3=20MR=20sequence,=20W63AH6NKB=20type-force)=20?=
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=?UTF-8?q?=E2=80=94=20ported=20from=20tobunto=20X2000?=
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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---
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arch/mips/cpu/xburst2/ddr_innophy.c | 20 ++++++++++++++++++++
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arch/mips/cpu/xburst2/ddr_reg_data.h | 2 ++
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2 files changed, 22 insertions(+)
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diff --git a/arch/mips/cpu/xburst2/ddr_innophy.c b/arch/mips/cpu/xburst2/ddr_innophy.c
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index 5257e3a..e08a5df 100755
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--- a/arch/mips/cpu/xburst2/ddr_innophy.c
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+++ b/arch/mips/cpu/xburst2/ddr_innophy.c
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@@ -454,6 +454,21 @@ static void ddrc_dfi_init(enum ddr_type type, int bypass)
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ddr_writel(DDRC_LMR_MR(2), DDRC_LMR); //MR2
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ddr_writel(DDRC_LMR_MR(3), DDRC_LMR); //MR3
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ddr_writel(DDRC_DLMR_VALUE | DDRC_LMR_START | DDRC_LMR_CMD_ZQCL_CS0, DDRC_LMR); //ZQCL
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+#undef DDRC_LMR_MR
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+ break;
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+ case LPDDR3:
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+ /* LPDDR3 MR sequence - ported from tobunto/u-boot X2000 (matches the vendor
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+ * disc_spl.bin trace): MR63,10,1,2,3,11 each followed by mdelay(1); no ZQ. */
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+#define DDRC_LMR_MR(n) \
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+ DDRC_DLMR_VALUE | DDRC_LMR_START | DDRC_LMR_CMD_LMR | \
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+ ((DDR_MR##n##_VALUE & 0xff) << 24) | \
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+ (((DDR_MR##n##_VALUE >> 8) & 0xff) << (16))
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+ ddr_writel(DDRC_LMR_MR(63), DDRC_LMR); mdelay(1); //set MRS reset
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+ ddr_writel(DDRC_LMR_MR(10), DDRC_LMR); mdelay(1); //set IO calibration
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+ ddr_writel(DDRC_LMR_MR(1), DDRC_LMR); mdelay(1); //set MR1
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+ ddr_writel(DDRC_LMR_MR(2), DDRC_LMR); mdelay(1); //set MR2
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+ ddr_writel(DDRC_LMR_MR(3), DDRC_LMR); mdelay(1); //set MR3
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+ ddr_writel(DDRC_LMR_MR(11), DDRC_LMR); mdelay(1); //set MR11
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#undef DDRC_LMR_MR
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break;
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default:
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@@ -556,6 +571,11 @@ void sdram_init(void)
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soc_ddr_init();
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type = get_ddr_type();
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+ /* Snowsky Disc = Winbond W63AH6NKB-BI LPDDR3. The controller CFG.TYPE field reads as
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+ * LPDDR2(5) for this part (the vendor SPL dispatches on the logical record type=3, not
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+ * CFG.TYPE), so force the LPDDR3 MR sequence here. Only ddrc_dfi_init consumes `type`
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+ * (the X2000 prev_ddr_init hook is a no-op). */
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+ type = LPDDR3;
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clk_set_rate(DDR, gd->arch.gi->ddrfreq);
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if(ddr_hook && ddr_hook->prev_ddr_init)
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ddr_hook->prev_ddr_init(type);
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diff --git a/arch/mips/cpu/xburst2/ddr_reg_data.h b/arch/mips/cpu/xburst2/ddr_reg_data.h
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index 4878267..b48575f 100755
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--- a/arch/mips/cpu/xburst2/ddr_reg_data.h
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+++ b/arch/mips/cpu/xburst2/ddr_reg_data.h
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@@ -27,6 +27,7 @@ struct ddr_registers
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uint32_t ddr_mr2;
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uint32_t ddr_mr3;
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uint32_t ddr_mr10;
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+ uint32_t ddr_mr11;
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uint32_t ddr_mr63;
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uint32_t ddr_chip0_size;
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uint32_t ddr_chip1_size;
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@@ -59,6 +60,7 @@ extern struct ddr_registers *g_ddr_param;
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#define DDR_MR2_VALUE g_ddr_param->ddr_mr2
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#define DDR_MR3_VALUE g_ddr_param->ddr_mr3
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#define DDR_MR10_VALUE g_ddr_param->ddr_mr10
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+#define DDR_MR11_VALUE g_ddr_param->ddr_mr11
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#define DDR_MR63_VALUE g_ddr_param->ddr_mr63
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#define DDR_CHIP_0_SIZE g_ddr_param->ddr_chip0_size
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#define DDR_CHIP_1_SIZE g_ddr_param->ddr_chip1_size
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--
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2.43.0
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