b0hemia
e0bc4785e9
Flashes the diskOS custom UI onto the FiiO Snowsky Disc over Ingenic mask-ROM USB, building the image from your own stock firmware. Runs from source via install.sh.
53 lines
2.4 KiB
Diff
53 lines
2.4 KiB
Diff
From 7caf048bae01c31460d4d675a52823e5b62ff091 Mon Sep 17 00:00:00 2001
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From: b0hemia <50309975+b0hemia@users.noreply.github.com>
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Date: Tue, 25 Aug 2026 01:52:48 +1000
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Subject: [PATCH 8/8] spl: robust WDT disable (clear TCER.TCEN + TSSR) + drop
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dynamic-calib sweep (flash-failure root cause)
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---
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arch/mips/cpu/xburst2/ddr_innophy.c | 8 +++++++-
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arch/mips/cpu/xburst2/x2000/soc.c | 8 +++++++-
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2 files changed, 14 insertions(+), 2 deletions(-)
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diff --git a/arch/mips/cpu/xburst2/ddr_innophy.c b/arch/mips/cpu/xburst2/ddr_innophy.c
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index 4c7b921..b78c02b 100755
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--- a/arch/mips/cpu/xburst2/ddr_innophy.c
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+++ b/arch/mips/cpu/xburst2/ddr_innophy.c
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@@ -626,7 +626,13 @@ void sdram_init(void)
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ddr_hook->post_ddr_init(type);
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ddr_diag_stage(8);
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- get_dynamic_calib_value(rate);
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+ /* Dropped get_dynamic_calib_value(rate): the vendor SPL does NOT do this multi-rate
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+ * DVFS calibration sweep. Its result table is never consumed by the burner/writer path,
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+ * and the extra frequency transitions + retraining can leave a marginal final PHY
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+ * calibration that fails under the writer's sustained full-DRAM load (2026-08-25). The
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+ * single ddrp_calibration() above already calibrates at the final 400MHz. */
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+ /* get_dynamic_calib_value(rate); */
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+ (void)rate;
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if(DDRC_AUTOSR_EN_VALUE) {
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/* ddr_writel(DDRC_AUTOSR_CNT_VALUE, DDRC_AUTOSR_CNT); */
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diff --git a/arch/mips/cpu/xburst2/x2000/soc.c b/arch/mips/cpu/xburst2/x2000/soc.c
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index ab9e437..6ea4b83 100755
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--- a/arch/mips/cpu/xburst2/x2000/soc.c
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+++ b/arch/mips/cpu/xburst2/x2000/soc.c
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@@ -83,7 +83,13 @@ void board_init_f(ulong dummy)
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*(volatile unsigned int *)0xb0000020 = 0; //clk gate enable.
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*(volatile unsigned int *)0xb0000028 = 0; //clk gate enable.
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- *(volatile unsigned int *)0xb000202c |= 1 << 16; // wdt disable.
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+ /* Disable the watchdog ROBUSTLY (match the vendor SPL + the tree's hw_watchdog_disable):
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+ * clear WDT_TCER.TCEN FIRST, then stop the WDT clock via TCU_TSSR (write-1, no RMW).
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+ * The old code stopped only the clock, leaving the counter armed - if the mask ROM
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+ * re-clocks it after we return, it fires and resets the device mid-flash (root cause of
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+ * the 2026-08-25 flash failure: device reset ~36min into the writer and again idle). */
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+ *(volatile unsigned int *)0xb0002004 &= ~(1u << 0); // WDT_TCER.TCEN = 0 (disable counter)
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+ *(volatile unsigned int *)0xb000202c = (1u << 16); // TCU_TSSR: stop WDT clock
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/* Init uart first */
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enable_uart_clk();
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--
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2.43.0
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