b0hemia
e0bc4785e9
Flashes the diskOS custom UI onto the FiiO Snowsky Disc over Ingenic mask-ROM USB, building the image from your own stock firmware. Runs from source via install.sh.
145 lines
5.1 KiB
Diff
145 lines
5.1 KiB
Diff
From eb05eaef0f7dac0fb1f166f88d69e1b895eb2e1a Mon Sep 17 00:00:00 2001
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From: b0hemia <50309975+b0hemia@users.noreply.github.com>
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Date: Mon, 24 Aug 2026 23:46:16 +1000
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Subject: [PATCH 4/8] ddr: bound clk.c DDR-clock polls + constrain
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dynamic-calib div; board_init_f breadcrumbs
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---
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arch/mips/cpu/xburst2/ddr_innophy.c | 1 +
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arch/mips/cpu/xburst2/x2000/clk.c | 6 +++---
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arch/mips/cpu/xburst2/x2000/soc.c | 22 +++++++++++++++++++++
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arch/mips/include/asm/arch-x2000/ddr_diag.h | 17 ++++++++++++++++
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4 files changed, 43 insertions(+), 3 deletions(-)
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create mode 100644 arch/mips/include/asm/arch-x2000/ddr_diag.h
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diff --git a/arch/mips/cpu/xburst2/ddr_innophy.c b/arch/mips/cpu/xburst2/ddr_innophy.c
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index 91cf6a3..c9b19f8 100755
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--- a/arch/mips/cpu/xburst2/ddr_innophy.c
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+++ b/arch/mips/cpu/xburst2/ddr_innophy.c
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@@ -563,6 +563,7 @@ static void get_dynamic_calib_value(unsigned int rate)
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ddr_calibration(&dcv[cur_div], cur_div);
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break;
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}
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+ if(div > 0xf) { ddr_diag_fail(60 /*calib div overflow - bad DDR rate*/, (unsigned int)rate); break; }
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dcv[div].rate = drate;
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dcv[div].refcnt = get_refcnt_value(div);
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ddr_calibration(&dcv[div], div);
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diff --git a/arch/mips/cpu/xburst2/x2000/clk.c b/arch/mips/cpu/xburst2/x2000/clk.c
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index c700a03..30764b6 100755
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--- a/arch/mips/cpu/xburst2/x2000/clk.c
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+++ b/arch/mips/cpu/xburst2/x2000/clk.c
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@@ -27,6 +27,7 @@
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#include <asm/gpio.h>
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#include <asm/arch/cpm.h>
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#include <asm/arch/clk.h>
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+#include <asm/arch/ddr_diag.h>
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#include <generated/clk_reg_values.h>
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DECLARE_GLOBAL_DATA_PTR;
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@@ -68,7 +69,7 @@ void clk_prepare(void)
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/*set div max*/
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regval |= cgusetting[i].val;
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writel(regval, reg);
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- while (readl(reg) & (1 << cgusetting[i].busy));
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+ DDR_BOUND(!(readl(reg) & (1 << cgusetting[i].busy)), 4 /*cgu init busy*/, readl(reg));
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} else {
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regval &= ~(1 << cgusetting[i].ce);
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writel(regval, reg);
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@@ -244,8 +245,7 @@ void clk_set_rate(int clk_id, unsigned long rate)
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regval &= ~(3 << cgu->stop | 0xff);
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regval |= ((1 << cgu->ce) | cdr);
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writel(regval, reg);
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- while (readl(reg) & (1 << cgu->busy))
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- ;
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+ DDR_BOUND(!(readl(reg) & (1 << cgu->busy)), 5 /*DDR clk busy (clk_set_rate)*/, readl(reg));
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#ifdef DUMP_CGU_SELECT
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printf("%s(0x%x) :0x%x\n",clk_name[clk_id] ,reg, readl(reg));
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#endif
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diff --git a/arch/mips/cpu/xburst2/x2000/soc.c b/arch/mips/cpu/xburst2/x2000/soc.c
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index 54ff3b7..6b96c5b 100755
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--- a/arch/mips/cpu/xburst2/x2000/soc.c
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+++ b/arch/mips/cpu/xburst2/x2000/soc.c
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@@ -67,11 +67,23 @@ extern void ddr_test_refresh(unsigned int start_addr, unsigned int end_addr);
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extern void flush_cache_all(void);
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+/* DIAG: breadcrumb record @0xb24017c0 (shared with ddr_innophy.c). Set 1 to early-return
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+ * before sdram_init to prove the mask-ROM return path works in isolation. */
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+#define DIAG_SKIP_SDRAM 0
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+#define BIF_CRUMB(s) do { *(volatile unsigned int*)0xb24017c4 = (s); __asm__ __volatile__("sync"); } while(0)
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+
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void board_init_f(ulong dummy)
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{
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/* Set global data pointer */
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gd = &gdata;
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+ /* DIAG: mark that we reached board_init_f (magic + stage 0xF0) */
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+ *(volatile unsigned int*)0xb24017c0 = 0xD1A6C0DEu;
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+ *(volatile unsigned int*)0xb24017c8 = 0;
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+ *(volatile unsigned int*)0xb24017cc = 0;
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+ *(volatile unsigned int*)0xb24017d0 = 0;
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+ BIF_CRUMB(0xF0);
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+
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/* Setup global info */
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#ifndef CONFIG_BURNER
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gd->arch.gi = &ginfo;
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@@ -80,6 +92,7 @@ void board_init_f(ulong dummy)
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#endif
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gpio_init();
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+ BIF_CRUMB(0xF1);
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*(volatile unsigned int *)0xb0000020 = 0; //clk gate enable.
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*(volatile unsigned int *)0xb0000028 = 0; //clk gate enable.
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@@ -93,15 +106,24 @@ void board_init_f(ulong dummy)
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#endif
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debug("Timer init\n");
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timer_init();
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+ BIF_CRUMB(0xF2);
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debug("CLK stop\n");
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// clk_prepare();
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debug("PLL init\n");
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pll_init();
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+ BIF_CRUMB(0xF3);
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debug("CLK init\n");
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clk_init();
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+ BIF_CRUMB(0xF4);
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+
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+#if DIAG_SKIP_SDRAM
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+ /* DIAG: return before DDR to test the mask-ROM return path in isolation. */
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+ BIF_CRUMB(0xFE);
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+ return;
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+#endif
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debug("SDRAM init\n");
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sdram_init();
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diff --git a/arch/mips/include/asm/arch-x2000/ddr_diag.h b/arch/mips/include/asm/arch-x2000/ddr_diag.h
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new file mode 100644
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index 0000000..68654ec
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--- /dev/null
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+++ b/arch/mips/include/asm/arch-x2000/ddr_diag.h
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@@ -0,0 +1,17 @@
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+#ifndef _ASM_ARCH_DDR_DIAG_H
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+#define _ASM_ARCH_DDR_DIAG_H
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+/* Shared DDR bring-up breadcrumb record @0xb24017c0 (TCSM pad below the start.S return
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+ * shim scratch at 0x17f0). usbboot uploads it after the SPL returns to the mask ROM.
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+ * Layout: [0]=magic [1]=stage [2]=first fail id [3]=status@fail [4]=fail count */
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+#define DDR_DIAG ((volatile unsigned int *)0xb24017c0)
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+#define DDR_DIAG_MAGIC 0xD1A6C0DEu
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+#define ddr_diag_fail_raw(id, status) do { \
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+ if(DDR_DIAG[2]==0){ DDR_DIAG[2]=(unsigned int)(id); DDR_DIAG[3]=(unsigned int)(status); } \
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+ DDR_DIAG[4]++; __asm__ __volatile__("sync"); \
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+ } while(0)
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+/* bounded busy-wait: wait for (cond); on ~1e6-iter timeout record (id,statusexpr) and stop. */
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+#define DDR_BOUND(cond, id, statusexpr) do { \
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+ unsigned int _bt = 1000000u; \
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+ while(!(cond)) { if(!--_bt){ ddr_diag_fail_raw((id), (statusexpr)); break; } } \
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+ } while(0)
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+#endif
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--
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2.43.0
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