b0hemia
e0bc4785e9
Flashes the diskOS custom UI onto the FiiO Snowsky Disc over Ingenic mask-ROM USB, building the image from your own stock firmware. Runs from source via install.sh.
50 lines
1.8 KiB
Diff
50 lines
1.8 KiB
Diff
From 26f15d13ea9b7e92eaf2326909b202799797f440 Mon Sep 17 00:00:00 2001
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From: b0hemia <50309975+b0hemia@users.noreply.github.com>
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Date: Mon, 24 Aug 2026 23:52:48 +1000
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Subject: [PATCH 6/8] ddr: fix PHY PLL divisors 20/5 -> 8/4 for W63AH6NKB
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LPDDR3 400MHz (calibration root cause)
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---
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arch/mips/cpu/xburst2/ddr_innophy.c | 15 ++++++---------
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1 file changed, 6 insertions(+), 9 deletions(-)
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diff --git a/arch/mips/cpu/xburst2/ddr_innophy.c b/arch/mips/cpu/xburst2/ddr_innophy.c
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index b394dad..4c7b921 100755
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--- a/arch/mips/cpu/xburst2/ddr_innophy.c
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+++ b/arch/mips/cpu/xburst2/ddr_innophy.c
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@@ -247,25 +247,22 @@ static void ddrp_pll_init(void)
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{
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unsigned int val;
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+ /* PHY PLL divisors for W63AH6NKB LPDDR3 @400MHz: FBDIV=8, PDIV=4 (from tobunto X2000,
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+ * matches the vendor SPL). The tree's stock 20/5 sets the wrong PHY clock -> training
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+ * (CALIB_DONE) never converges. */
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val = ddr_readl(DDRP_INNOPHY_PLL_FBDIV);
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val &= ~(0xff);
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- val |= 0x14;
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+ val |= 0x8;
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ddr_writel(val, DDRP_INNOPHY_PLL_FBDIV);
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val = ddr_readl(DDRP_INNOPHY_PLL_PDIV);
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val &= ~(0xff);
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- val |= 0x5;
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+ val |= 4;
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ddr_writel(val, DDRP_INNOPHY_PLL_PDIV);
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- /* ddr_writel(0x14, DDRP_INNOPHY_PLL_FBDIV); */
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- /* ddr_writel(0x5, DDRP_INNOPHY_PLL_PDIV); */
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-#ifdef DEBUG_READ_WRITE
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+ /* toggle PLLPDEN via RMW (preserve other PLL_CTRL bits), as tobunto/vendor do */
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ddr_writel(ddr_readl(DDRP_INNOPHY_PLL_CTRL) | DDRP_PLL_CTRL_PLLPDEN, DDRP_INNOPHY_PLL_CTRL);
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ddr_writel(ddr_readl(DDRP_INNOPHY_PLL_CTRL) & ~DDRP_PLL_CTRL_PLLPDEN, DDRP_INNOPHY_PLL_CTRL);
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-#else
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- ddr_writel(DDRP_PLL_CTRL_PLLPDEN, DDRP_INNOPHY_PLL_CTRL);
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- ddr_writel(0, DDRP_INNOPHY_PLL_CTRL);
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-#endif
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DDR_BOUND(ddr_readl(DDRP_INNOPHY_PLL_LOCK) & (1 << 3), 10 /*PLL_LOCK*/, ddr_readl(DDRP_INNOPHY_PLL_LOCK));
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}
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--
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2.43.0
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